Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 2nd Edition (The International Series in Engineering and Computer Science)
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Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, 2nd Edition (The International Series in Engineering and Computer Science)
Verilog HDL 数字设计与综合 第二版 - Samir Palnitkar 著 夏宇闻 等译
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Analog Behavioral Modeling with the Verilog-A Language
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FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version
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FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version
Verilog® Quicstart: A Practical Guide to Simulation and Synthesis in Verilog
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Verilog® Quicstart: A Practical Guide to Simulation and Synthesis in Verilog
The Verilog PLI Handbook: A Users Guide and Comprehensive Reference on the Verilog Programming Language Interface
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The Verilog PLI Handbook: A Users Guide and Comprehensive Reference on the Verilog Programming Language Interface
Smith VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C
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Smith VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C
EDA 技术实用教程 VERILOG HDL 版
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Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
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Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog
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Verilog Quickstart: A Practical Guide to Simulation and Synthesis in Verilog
Verilog HDL Synthesis A Practical Primer
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Verilog HDL Synthesis A Practical Primer
Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical Institute
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Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical Institute
Verilog Hardware Description Language. IEEE 1364
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Verilog Hardware Description Language. IEEE 1364
Verilog HDL 硬件描述语言 第二版 - J. Bhasker 著 徐振林 等译
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Verilog HDL 硬件描述语言 第二版 - J. Bhasker 著 徐振林 等译
Verilog Coding for Logic Synthesis
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Verilog Coding for Logic Synthesis
Digital Computer Arithmetic Datapath Design Using Verilog HDL
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Digital Computer Arithmetic Datapath Design Using Verilog HDL